Simple Hardware for Fast Interprocessor Communication
Report ID: TR-242-90Author: Greenstreet, Mark R. / Li, Kai
Date: 1990-01-00
Pages: 12
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Abstract:
This paper presents a new approach for implementing point-to-point communication in multiprocessors: STARI, Self-Timed At Receiver's Input. STARI is a hybrid approach combining techniques from self-timed and synchronous designs. STARI designs are immune from clock-skew related problems and can operate faster than either purely synchronous or purely self-timed designs. Using a generic 2.0-mu CMOS process, transmission rates in excess of 250 Mbits/sec can be achieved for each wire connecting communicating processors.