Although transistor density continues to increase, power density is increasing each chip generation. Particularly in mobile devices, which have limited cooling options, these trends lead to "dark silicon" in which sustained chip performance is limited primarily by power rather than area. However, many mobile applications do not demand sustained performance; rather they comprise short bursts of computation in response to sporadic user activity.
To improve responsiveness for such applications, this talk describes "computational sprinting", in which the system activates otherwise powered-down cores for brief bursts of intense parallel computation. During a sprint the chip temporarily exceeds its sustainable thermal power budget to provide instantaneous throughput, after which the chip must return to nominal operation to cool down. To enable longer sprints, we describe a thermal design that incorporates phase-change materials to provide thermal capacitance. Results indicate that sprinting can both provide large improvements in responsiveness while actually saving energy due to race-to-idle effects.
Thomas Wenisch is an Associate Professor of Computer Science and Engineering at the University of Michigan, specializing in computer architecture. His prior research includes memory streaming for commercial server applications, multiprocessor memory systems, memory disaggregation, and rigorous sampling-based performance evaluation methodologies. His ongoing work focuses on computational sprinting, server and data center architectures, programming models for byte-addressable NVRAM, and architectures to enable hand-held 3D ultrasound. Wenisch received the NSF CAREER award in 2009. Prior to his academic career, Wenisch was a software developer at American Power Conversion, where he worked on data center thermal topology estimation. He received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University.